The present invention relates to a clock control system for use in information processing, digital communication processing and the like.
Some computer systems are single processor systems, having only one data processing unit, while others are multi-processor systems, having a plurality of such units. The basic machine cycle for the operation of these systems is determined by a clock (pulse) given from a clock supplying unit. Thus, in each of the systems referred to above, the basic machine cycle for operation is determined by either a clock given from only one clock supplying unit provided for a system or a clock selected from one of plural clock supplying units, one provided for each data processing unit. One such clock supplying unit is provided with a plurality of oscillators generating a clock (pulse) of different frequencies and with a selector for selecting one of these clock trains of different frequencies generated by these plural oscillators. Another clock supplying unit can generate clock signals in different cycles. For details of this type of unit, reference may be made to the specification of the U.S. Pat. No. 4,564,943. These units are used for early trouble-shooting of data processing units.
Trouble in a clock supplying unit in a system having only one such unit may invite system failure, and its consequences increase with the dimensions of the system.
Where a system has a plurality of clock supplying units, trouble in one of these units may also invite system failure, but a subsequent manual switchover to another clock supplying unit can reduce the occurring probability of system failure. However, as the switchover from the faulty clock supplying unit to a specific other clock supplying unit is manually achieved, the operational convenience is adversely affected. If, moreover, both the clock supplying unit and the plurality of oscillators provided for the unit have to be switched, the operation will be made correspondingly more complex.